JEDEC (the JEDEC Solid State Technology Association) is the global standards body that develops open specifications for semiconductor memory and packaging. It defines the electrical, mechanical and timing standards for technologies such as DRAM, DDR5, HBM and NAND flash, ensuring components from different manufacturers interoperate. JEDEC standards underpin the memory subsystems of virtually all modern computing infrastructure.
Overview
- Founded as the Joint Electron Device Engineering Council, JEDEC now operates as the JEDEC Solid State Technology Association under the umbrella of industry consortia.
- It publishes royalty-free standards developed through committee consensus among memory manufacturers, foundries and system integrators.
- JEDEC specifications cover signalling, timing, command sets, packaging form factors and reliability test methods (JESD documents).
- By fixing electrical and mechanical interfaces, JEDEC allows DRAM, flash and emerging memory parts from competing vendors to be drop-in compatible.
Key aspects
- DDR (double data rate) SDRAM generations: DDR3, DDR4 and DDR5 timing and voltage standards.
- High Bandwidth Memory (HBM) stacked-die specifications for accelerators and GPUs.
- NAND flash interface and Universal Flash Storage (UFS) command standards.
- JESD reliability and qualification test methods for solder, temperature cycling and data retention.
- Module form factors such as DIMM, SO-DIMM and embedded MultiMediaCard layouts.
Applications
- Memory modules in servers, laptops and mobile devices that must interoperate across suppliers.
- Accelerator and GPU memory stacks (HBM) standardised for AI and HPC workloads.
- Solid-state storage controllers conforming to flash interface standards.
- Data-centre procurement relying on second-source compatibility to avoid supply lock-in.